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  general description the MAX7032 crystal-based, fractional-n transceiver is designed to transmit and receive ask/ook or fsk data in the 300mhz to 450mhz frequency range with data rates up to 33kbps (manchester encoded) or 66kbps (nrz encoded). this device generates a typi- cal output power of +10dbm into a 50 ? load, and exhibits typical sensitivities of -114dbm for ask data and -110dbm for fsk data. the MAX7032 features sep- arate transmit and receive pins (paout and lnain) and provides an internal rf switch that can be used to connect the transmit and receive pins to a common antenna. the MAX7032 transmit frequency is generated by a 16- bit, fractional-n, phase-locked loop (pll), while the receiver? local oscillator (lo) is generated by an inte- ger-n pll. this hybrid architecture eliminates the need for separate transmit and receive crystal reference oscillators because the fractional-n pll allows the transmit frequency to be set within 2khz of the receive frequency. the 12-bit resolution of the fractional-n pll allows frequency multiplication of the crystal frequency in steps of f xtal / 4096. retaining the fixed-n pll for the receiver avoids the higher current drain require- ments of a fractional-n pll and keeps the receiver cur- rent drain as low as possible. the fractional-n architecture of the MAX7032 transmit pll allows the transmit fsk signal to be programmed for exact frequency deviations, and completely eliminates the problems associated with oscillator-pulling fsk sig- nal generation. all frequency-generation components are integrated on-chip, and only a crystal, a 10.7mhz if filter, and a few discrete components are required to imple- ment a complete antenna/digital data solution. the MAX7032 is available in a small 5mm x 5mm, 32-pin, thin qfn package, and is specified to operate in the automotive -40? to +125? temperature range. applications 2-way remote keyless entry security systems home automation remote controls remote sensing smoke alarms garage door openers local telemetry systems features ? +2.1v to +3.6v or +4.5v to +5.5v single-supply operation ? single crystal transceiver ? user-adjustable 300mhz to 450mhz carrier frequency ? ask/ook and fsk modulation ? user-adjustable fsk frequency deviation through fractional-n pll register ? agile transmitter frequency synthesizer with f xtal / 4096 carrier-frequency spacing ? +10dbm output power into 50 ? load ? integrated tx/rx switch ? integrated transmit and receive pll, vco, and loop filter ? > 45db image rejection ? typical rf sensitivity* ask: -114dbm fsk: -110dbm ? selectable if bandwidth with external filter ? rssi output with high dynamic range ? autopolling low-power management ? < 12.5ma transmit-mode current ? < 6.7ma receive-mode current ? < 23.5a polling-mode current ? < 800na shutdown current ? fast-on startup feature, < 250s ? small 32-pin, thin qfn package MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll ________________________________________________________________ maxim integrated products 1 ordering information 19-3685; rev 0; 5/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package pkg code MAX7032atj -40? to +125? 32 thin qfn-ep** t3255-3 *0.2% ber, 4kbps manchester-encoded data, 280khz if bw, average rf power ** ep = exposed paddle. pin configuration, typical application circuit, and functional diagram appear at end of data sheet.
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. hv in to gnd..........................................................-0.3v to +6.0v pav dd , av dd , dv dd to gnd ................................-0.3v to +4.0v enable, t/ r , data, cs , dio, sclk, clkout to gnd ......................................................-0.3v to (hv in + 0.3v) all other pins to gnd ...............................-0.3v to (_v dd + 0.3v) continuous power dissipation (t a = +70?) 32-pin thin qfn (derate 21.3mw/? above +70?)....1702mw operating temperature range .........................-40? to +125? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? dc electrical characteristics ( typical application circuit , 50 ? system impedance, av dd = dv dd = p avdd = hv in = +2.1v to +3.6v, f rf = 300mhz to 450mhz, t a = -40? to +125?, unless otherwise noted. typical values are at av dd = dv dd = pav dd = hv in = +2.7v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units supply voltage (3v mode) v dd hv in , pav dd , av dd , and dv dd connected to power supply 2.1 2.7 3.6 v supply voltage (5v mode) hv in pav dd , av dd , and dv dd unconnected from hv in , but connected together 4.5 5.0 5.5 v f rf = 315mhz 3.5 5.4 transmit mode, pa off, v data at 0% duty cycle (ask) (note 2) f rf = 434mhz 4.3 6.7 f rf = 315mhz 7.6 12.3 transmit mode, v data at 50% duty cycle (ask) (notes 3, 4) f rf = 434mhz 8.4 13.6 f rf = 315mhz (note 4) 11.6 19.1 transmit mode, v data at 100% duty cycle (fsk) f rf = 434mhz (note 2) 12.4 20.4 ma receiver (ask 315mhz) 6.1 7.9 receiver (ask 434mhz) 6.4 8.3 receiver (fsk 315mhz) 6.4 8.4 receiver (fsk 434mhz) 6.7 8.7 ma drx (3v mode) 23.4 77.3 drx (5v mode) 67.2 94.4 deep-sleep (3v mode) 0.8 8.8 t a < +85?, typ at +25? (note 4) deep-sleep (5v mode) 2.4 10.9 ? receiver (ask 315mhz) 6.4 8.2 receiver (ask 434mhz) 6.7 8.4 receiver (fsk 315mhz) 6.8 8.7 receiver (fsk 434mhz) 7.0 8.8 ma drx (3v mode) 33.5 103.0 drx (5v mode) 82.3 116.1 deep-sleep (3v mode) 8.0 34.2 supply current i dd t a < +125? typ at +125? (note 2) deep-sleep (5v mode) 14.9 39.3 ? voltage regulator v reg hv in = 5v, i load = 15ma 3.0 v
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll _______________________________________________________________________________________ 3 dc electrical characteristics (continued) ( typical application circuit , 50 ? system impedance, av dd = dv dd = p avdd = hv in = +2.1v to +3.6v, f rf = 300mhz to 450mhz, t a = -40? to +125?, unless otherwise noted. typical values are at av dd = dv dd = pav dd = hv in = +2.7v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units digital i/o input high threshold v ih (note 2) 0.9 x hv in v input low threshold v il (note 2) 0.1 x hv in v pulldown sink current sclk, enable, t/ r , data (hv in = 5.5v) 20 ? pullup source current dio, cs (hv in = 5.5v) 20 ? output-low voltage v ol i sink = 500? 0.15 v output-high voltage v oh i source = 500? hv in - 0.26 v ac electrical characteristics ( typical application circuit , 50 ? system impedance, av dd = dv dd = pav dd = hv in = +2.1v to +3.6v, f rf = 300mhz to 450mhz, t a = -40? to +125?, unless otherwise noted. typical values are at pav dd = av dd = dv dd = hv in = +2.7v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units general characteristics frequency range 300 450 mhz maximum input level p rfin 0dbm f rf = 315mhz (note 6) 32 transmit efficiency 100% duty cycle f rf = 434mhz (note 6) 30 % f rf = 315mhz (note 6) 24 transmit efficiency 50% duty cycle f rf = 434mhz (note 6) 22 % enable or t/ r transition low to high, transmitter frequency settled to within 50khz of the desired carrier 200 enable or t/ r transition low to high, transmitter frequency settled to within 5khz of the desired carrier 350 power-on time t on enable transition low to high, or t/ r transition high to low receiver startup time (note 5) 250 ? receiver ask (315mhz) -114 ask (434mhz) -113 fsk (315mhz) -110 sensitivity 0.2% ber, 4kbps manchester data rate, 280khz if bw, ?0khz fsk deviation, average power fsk (434mhz) -107 dbm image rejection (note 8) 46 db
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll 4 _______________________________________________________________________________________ ac electrical characteristics (continued) ( typical application circuit , 50 ? system impedance, av dd = dv dd = pav dd = hv in = +2.1v to +3.6v, f rf = 300mhz to 450mhz, t a = -40? to +125?, unless otherwise noted. typical values are at pav dd = av dd = dv dd = hv in = +2.7v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units power amplifier t a = +25? (note 4) 4.6 10.0 15.5 t a = +125?, av dd = dv dd = hv in = pav dd = +2.1v (note 2) 3.9 6.7 output power p out t a = -40?, av dd = dv dd = hv in = pav dd = +3.6v (note 4) 13.1 15.8 dbm modulation depth 82 db maximum carrier harmonics with output-matching network -40 dbc reference spur -50 dbc phase-locked loop transmit vco gain k vco 340 mhz/v 10khz offset, 200khz loop bw -68 transmit pll phase noise 1mhz offset, 200khz loop bw -98 dbc/hz receive vco gain 340 mhz/v 10khz offset, 500khz loop bw -80 receive pll phase noise 1mhz offset, 500khz loop bw -90 dbc/hz transmit pll 200 loop bandwidth receive pll 500 khz minimum transmit frequency step f xtal / 4096 khz reference frequency input level 0.5 v p-p programmable divider range in transmit mode (note 4) 20 27 low-noise amplifier/mixer (note 9) f rf = 315mhz 1 - j4.7 lna input impedance z inlna normalized to 50 ? f rf = 434mhz 1 - j3.3 f rf = 315mhz 50 high-gain state f rf = 434mhz 45 f rf = 315mhz 13 voltage-conversion gain low-gain state f rf = 434mhz 9 db high-gain state -42 input-referred 3rd-order intercept point iip3 low-gain state -6 dbm mixer output impedance 330 ? lo signal feedthrough to antenna -100 dbm rssi input impedance 330 ? operating frequency f if 10.7 mhz 3db bandwidth 10 mhz
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll _______________________________________________________________________________________ 5 ac electrical characteristics (continued) ( typical application circuit , 50 ? system impedance, av dd = dv dd = pav dd = hv in = +2.1v to +3.6v, f rf = 300mhz to 450mhz, t a = -40? to +125?, unless otherwise noted. typical values are at pav dd = av dd = dv dd = hv in = +2.7v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units gain 15 mv/db fsk demodulator conversion gain 2.0 mv/khz analog baseband maximum data filter bandwidth 50 khz maximum data slicer bandwidth 100 khz maximum peak detector bandwidth 50 khz manchester coded 33 maximum data rate nrz 66 kbps crystal oscillator crystal frequency f xtal (f rf - 10.7) / 24 mhz maximum crystal inductance 50 mh frequency pulling by v dd 2 ppm/v crystal load capacitance (note 7) 4.5 pf serial interface timing characteristics (see figure 7) minimum sclk setup to falling edge of cs t sc 30 ns minimum cs falling edge to sclk rising-edge setup time t css 30 ns minimum cs idle time t csi 125 ns minimum cs period t cs 2.125 ? maximum sclk falling edge to data valid delay t do 80 ns minimum data valid to sclk rising-edge setup time t ds 30 ns minimum data valid to sclk rising-edge hold time t dh 30 ns minimum sclk high pulse width t ch 100 ns minimum sclk low pulse width t cl 100 ns minimum cs rising edge to sclk rising-edge hold time t csh 30 ns maximum cs falling edge to output enable time t dv 25 ns maximum cs rising edge to output disable time t tr 25 ns
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll 6 _______________________________________________________________________________________ ac electrical characteristics (continued) ( typical application circuit , 50 ? system impedance, av dd = dv dd = pav dd = hv in = +2.1v to +3.6v, f rf = 300mhz to 450mhz, t a = -40? to +125?, unless otherwise noted. typical values are at pav dd = av dd = dv dd = hv in = +2.7v, t a = +25?, unless otherwise noted.) (note 1) note 1: supply current, output power, and efficiency are greatly dependent on board layout and paout match. note 2: 100% tested at t a = +125?. guaranteed by design and characterization overtemperature. note 3: 50% duty cycle at 10khz ask data (manchester coded). note 4: guaranteed by design and characterization. not production tested. note 5: time for final signal detection; does not include baseband filter settling. note 6: efficiency = p out / (v dd x i dd ). note 7: dependent on pc board trace capacitance. note 8: the oscillator register (0x05) is set to the nearest integer result of f xtal / 100khz (see the oscillator frequency register sec- tion). note 9: input impedance is measured at the lnain pin. note that the impedance at 315mhz includes the 12nh inductive degenera- tion from the lna source to ground. the impedance at 434mhz includes a 10nh inductive degeneration connected from the lna source to ground. the equivalent input circuit is approximately 50 ? in series with ~ 2.2pf. the voltage conversion is measured with the lna input matching inductor, the degeneration inductor, and the lna/mixer tank in place, and does not include the if filter insertion loss. typical operating characteristics ( typical operating circuit , pav dd = av dd = dv dd = hv in = +3.0v, f rf = 433.92mhz, t a = +25?, if bw = 280khz, data rate = 4kbps manchester encoded, frequency deviation = ?0khz, ber = 0.2% average rf power, unless otherwise noted.) supply current vs. supply voltage (ask mode) MAX7032 toc01 supply voltage (v) supply current (ma) 3.3 3.0 2.7 2.4 5.8 6.0 6.2 6.4 6.6 6.8 7.0 5.6 2.1 3.6 t a = +85 c t a = +125 c t a = +25 c t a = -40 c supply current vs. rf frequency (ask mode) MAX7032 toc02a rf frequency (mhz) supply current (ma) 425 400 325 350 375 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.0 300 450 t a = +85 c t a = +125 c t a = +25 c t a = -40 c supply current vs. rf frequency (fsk mode) MAX7032 toc02b rf frequency (mhz) supply current (ma) 425 400 325 350 375 6.5 6.6 6.7 6.8 6.9 7.0 6.4 300 450 t a = +85 c t a = +125 c t a = +25 c t a = -40 c receiver
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll _______________________________________________________________________________________ 7 deep-sleep current vs. temperature MAX7032 toc03 temperature ( c) deep-sleep current ( a) 110 85 35 60 -10 -15 2 4 6 8 10 12 14 16 18 0 -40 v cc = +3.6v v cc = +3.0v v cc = +2.1v bit-error rate vs. average input power (ask data) max7030 toc04 average input power (dbm) bit-error rate (%) -113 -115 -117 -119 0.1 1 10 100 0.01 -121 -111 f rf = 434mhz f rf = 315mhz 0.2% ber bit-error rate vs. average input power (fsk data) MAX7032 toc05 average input power (dbm) bit-error rate (%) -108 -106 -110 -112 -114 0.1 1 10 100 0.01 -116 -104 f rf = 434mhz 0.2% ber f rf = 315mhz sensitivity (dbm) -117 -114 -111 -108 -105 -102 -120 sensitivity vs. temperature (ask data) MAX7032 toc06 temperature ( c) 110 85 60 35 10 -15 -40 f rf = 434mhz f rf = 315mhz sensitivity (dbm) -110 -108 -106 -104 -102 -100 -112 sensitivity vs. temperature (fsk data) MAX7032 toc07 temperature ( c) 110 85 60 35 10 -15 -40 f rf = 434mhz f rf = 315mhz sensitivity vs. frequency deviation (fsk data) MAX7032 toc08 frequency deviation (khz) sensitivity (dbm) 10 -106 -104 -102 -100 -98 -96 -94 -108 1 100 rssi vs. rf input power MAX7032 toc09 rf input power (dbm) rssi (v) -10 -30 -70 -50 -90 -110 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 -130 10 low-gain mode high-gain mode agc switch point agc hysteresis: 3db rssi and delta vs. if input power MAX7032 toc10 if input power (dbm) rssi (v) -10 -30 -50 -70 0.3 0.6 0.9 1.2 1.5 1.8 2.1 0 -90 10 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 -3.5 delta (%) rssi delta typical operating characteristics (continued) ( typical operating circuit , pav dd = av dd = dv dd = hv in = +3.0v, f rf = 433.92mhz, t a = +25?, if bw = 280khz, data rate = 4kbps manchester encoded, frequency deviation = ?0khz, ber = 0.2% average rf power, unless otherwise noted.) receiver
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll 8 _______________________________________________________________________________________ fsk demodulator output vs. if frequency MAX7032 toc11 if frequency (mhz) fsk demodulator output (v) 10.9 10.8 10.7 10.6 10.5 0.4 0.8 1.2 1.6 0 10.4 11.0 system gain vs. if frequency MAX7032 toc12 if frequency (mhz) system gain (dbm) 25 20 15 10 5 -10 0 10 20 30 40 50 -20 030 lower sideband upper sideband from rfin to mixout f rf = 434mhz 48db image rejection image rejection vs. temperature MAX7032 toc13 image rejection (db) 44 46 48 42 temperature ( c) 110 85 60 35 10 -15 -40 f rf = 434mhz f rf = 315mhz normalized if gain vs. if frequency MAX7032 toc14 if frequency (mhz) normalized if gain (db) 10 -16 -12 -8 -4 0 -20 1 100 s11 vs. rf frequency MAX7032 toc15 rf frequency (mhz) s11 (db) 450 400 350 300 250 -18 -12 -6 0 -24 200 500 433.92mhz s11 smith plot of rfin MAX7032 toc16 434mhz 500mhz 400mhz input impedance vs. inductive degeneration MAX7032 toc17 inductive degeneration (nh) real impedance ( ? ) 10 30 40 50 60 70 80 90 20 imaginary impedance ( ? ) -280 -270 -260 -250 -240 -230 -220 -290 1 100 f rf = 315mhz imaginary impedance real impedance input impedance vs. inductive degeneration MAX7032 toc18 inductive degeneration (nh) real impedance ( ? ) 10 30 40 50 60 70 80 90 20 imaginary impedance ( ? ) -210 -200 -190 -180 -170 -160 -150 -220 1 100 f rf = 434mhz imaginary impedance real impedance typical operating characteristics (continued) ( typical operating circuit , pav dd = av dd = dv dd = hv in = +3.0v, f rf = 433.92mhz, t a = +25?, if bw = 280khz, data rate = 4kbps manchester encoded, frequency deviation = ?0khz, ber = 0.2% average rf power, unless otherwise noted.) receiver
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll _______________________________________________________________________________________ 9 phase noise vs. offset frequency MAX7032 toc19 offset frequency (hz) phase noise (dbc/hz) 1m 100k 10k 1k -110 -100 -90 -80 -70 -60 -50 -120 100 10m f rf = 315mhz phase noise vs. offset frequency MAX7032 toc20 offset frequency (hz) phase noise (dbc/hz) 1m 100k 10k 1k -110 -100 -90 -80 -70 -60 -50 -120 100 10m f rf = 434mhz supply current vs. supply voltage MAX7032 toc21 supply voltage (v) supply current (ma) 3.3 3.0 2.7 2.4 10 12 14 16 8 2.1 3.6 f rf = 315mhz pa on without envelope shaping t a = +85 c t a = +125 c t a = -40 c t a = +25 c supply current (ma) 2.5 3.0 3.5 4.0 5.0 4.5 5.5 6.0 2.0 supply current vs. supply voltage MAX7032 toc22 supply voltage (v) 3.3 3.0 2.7 2.4 2.1 3.6 f rf = 315mhz pa off t a = +85 c t a = +125 c t a = -40 c t a = +25 c supply current vs. supply voltage MAX7032 toc23 supply voltage (v) supply current (ma) 3.3 3.0 2.7 2.4 11 13 15 17 9 2.1 3.6 f rf = 434mhz pa on without envelope shaping t a = +85 c t a = +125 c t a = -40 c t a = +25 c supply current (ma) 3.0 3.5 4.0 5.0 4.5 5.5 6.0 supply current vs. supply voltage MAX7032 toc24 supply voltage (v) 3.3 3.0 2.7 2.4 2.1 3.6 f rf = 434mhz pa off t a = +85 c t a = +125 c t a = -40 c t a = +25 c supply current vs. output power MAX7032 toc25 average output power (dbm) supply current (ma) 6 2 -10 -6 -2 5 6 7 8 9 10 11 12 4 -14 10 f rf = 315mhz envelope shaping enabled pa on 50% duty cycle supply current vs. output power MAX7032 toc26 average output power (dbm) supply current (ma) 6 2 -2 -6 -10 6 7 8 9 10 11 12 13 14 5 -14 10 f rf = 434mhz envelope shaping enabled pa on 50% duty cycle typical operating characteristics (continued) ( typical operating circuit , pav dd = av dd = dv dd = hv in = +3.0v, f rf = 433.92mhz, t a = +25?, if bw = 280khz, data rate = 4kbps manchester encoded, frequency deviation = ?0khz, ber = 0.2% average rf power, unless otherwise noted.) receiver transmitter
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll 10 ______________________________________________________________________________________ supply current and output power vs. external resistor MAX7032 toc27-1 external resistor ( ? ) supply current (ma) 1k 100 1 10 4 6 8 10 12 14 16 18 2 0.1 10k -12 -8 -4 0 4 8 12 16 -16 output power (dbm) f rf = 315mhz pa on power current supply current and output power vs. external resistor MAX7032 toc27-2 external resistor ( ? ) supply current (ma) 1k 100 1 10 4 6 8 10 12 14 16 18 2 0.1 10k -12 -8 -4 0 4 8 12 16 -16 output power (dbm) f rf = 434mhz pa on power curent output power vs. supply voltage MAX7032 28-1 supply voltage (v) output power (dbm) 3.3 3.0 2.7 2.4 6 8 10 12 14 4 2.1 3.6 f rf = 315mhz pa on envelope shaping disabled t a = +85 c t a = +125 c t a = +25 c t a = -40 c output power vs. supply voltage MAX7032 28-2 supply voltage (v) output power (dbm) 3.3 3.0 2.7 2.4 6 8 10 12 14 4 2.1 3.6 f rf = 315mhz pa on envelope shaping enabled t a = +85 c t a = +125 c t a = +25 c t a = -40 c output power vs. supply voltage MAX7032 29-1 supply voltage (v) output power (dbm) 3.3 3.0 2.7 2.4 6 8 10 12 14 4 2.1 3.6 f rf = 434mhz pa on envelope shaping disabled t a = +85 c t a = +125 c t a = +25 c t a = -40 c output power vs. supply voltage MAX7032 29-2 supply voltage (v) output power (dbm) 3.3 3.0 2.7 2.4 8 10 12 14 6 2.1 3.6 f rf = 434mhz pa on envelope shaping enabled t a = +85 c t a = +125 c t a = +25 c t a = -40 c efficiency vs. supply voltage MAX7032 toc30 supply voltage (v) efficiency (%) 3.3 3.0 2.7 2.4 25 30 35 40 20 2.1 3.6 t a = +85 c t a = +125 c t a = +25 c t a = -40 c f rf = 315mhz pa on efficiency vs. supply voltage MAX7032 toc31 supply voltage (v) efficiency (%) 3.3 3.0 2.7 2.4 25 30 35 40 20 2.1 3.6 t a = +85 c t a = +125 c t a = +25 c t a = -40 c f rf = 434mhz pa on typical operating characteristics (continued) ( typical operating circuit , pav dd = av dd = dv dd = hv in = +3.0v, f rf = 433.92mhz, t a = +25?, if bw = 280khz, data rate = 4kbps manchester encoded, frequency deviation = ?0khz, ber = 0.2% average rf power, unless otherwise noted.) transmitter
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll ______________________________________________________________________________________ 11 efficiency vs. supply voltage MAX7032 toc32 supply voltage (v) efficiency (%) 3.3 3.0 2.7 2.4 15 20 25 30 10 2.1 3.6 t a = +85 c t a = +125 c t a = +25 c t a = -40 c f rf = 315mhz 50% duty cycle efficiency vs. supply voltage MAX7032 toc33 supply voltage (v) efficiency (%) 3.3 3.0 2.7 2.4 20 25 30 15 2.1 3.6 t a = +85 c t a = +125 c t a = +25 c t a = -40 c f rf = 434mhz 50% duty cycle phase noise vs. offset frequency MAX7032 toc34 offset frequency (hz) phase noise (dbc/hz) 1m 100k 10k 1k -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -140 100 10m f rf = 315mhz phase noise vs. offset frequency MAX7032 toc35 offset frequency (hz) phase noise (dbc/hz) 1m 100k 10k 1k -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -140 100 10m f rf = 434mhz reference spur magnitude vs. supply voltage MAX7032 toc36 supply voltage (v) reference spur magnitude (dbc) 3.3 3.0 2.7 2.4 -65 -60 -55 -50 -45 -40 -70 2.1 3.6 433.92mhz 315mhz frequency stability vs. supply voltage MAX7032 toc37 supply voltage (v) frequency stability (ppm) 3.3 3.0 2.7 2.4 -8 -6 -4 -2 0 2 4 6 8 10 -10 2.1 3.6 f rf = 315mhz f rf = 434mhz clkout spur magnitude vs. supply voltage MAX7032 toc38 supply voltage (v) clkout spur magnitude (dbc) 3.3 3.0 2.7 2.4 -64 -62 -60 -58 -56 -66 2.1 3.6 f clkout = f xtal / 8 f clkout = f xtal / 2 f clkout = f xtal / 4 f rf = 434mhz clkout spur = f rf f clkout 10pf load capacitance typical operating characteristics (continued) ( typical operating circuit , pav dd = av dd = dv dd = hv in = +3.0v, f rf = 433.92mhz, t a = +25?, if bw = 280khz, data rate = 4kbps manchester encoded, frequency deviation = ?0khz, ber = 0.2% average rf power, unless otherwise noted.) transmitter
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll 12 ______________________________________________________________________________________ pin description pin name function 1 pav dd power-amplifier supply voltage. bypass to gnd with 0.01? and 220pf capacitors placed as close to the pin as possible. 2 rout envelope-shaping output. rout controls the power-amplifier envelope? rise and fall times. connect rout to the pa pullup inductor or optional power-adjust resistor. bypass the inductor to gnd as close to the inductor as possible with 680pf and 220pf capacitors as shown in the typical application circuit . 3 tx/rx1 transmit/receive switch throw. drive t/ r high to short tx/rx1 to tx/rx2. drive t/ r low to disconnect tx/rx1 from tx/rx2. functionally identical to tx/rx2. 4 tx/rx2 transmit/receive switch pole. typically connected to ground. see the typical application circuit . 5 paout power-amplifier output. requires a pullup inductor to the supply voltage (or rout if envelope shaping is desired), which may be part of the output-matching network to an antenna. 6av dd analog power-supply voltage. av dd is connected to an on-chip +3.0v regulator in 5v operation. bypass av dd to gnd with 0.1? and 220pf capacitors placed as close to the pin as possible. 7 lnain low-noise amplifier input. must be ac-coupled. 8 lnasrc low-noise amplifier source for external inductive degeneration. connect an inductor to gnd to set the lna input impedance. 9 lnaout low-noise amplifier output. must be tied to av dd through a parallel lc tank filter. ac-couple to mixin+. 10 mixin+ noninverting mixer input. must be ac-coupled to the lna output. 11 mixin- inverting mixer input. bypass to av dd with a capacitor as close to lna lc tank filter as possible. 12 mixout 330 ? mixer output. connect to the input of the 10.7mhz filter. 13 ifin- inverting 330 ? if limiter amplifier input. bypass to gnd with a capacitor. 14 ifin+ noninverting 330 ? if limiter amplifier input. connect to the output of the 10.7mhz if filter. 15 pdmin minimum-level peak detector for demodulator output 16 pdmax maximum-level peak detector for demodulator output 17 ds- inverting data slicer input 18 ds+ noninverting data slicer input 19 op+ noninverting op amp input for the sallen-key data filter 20 df data filter feedback node. input for the feedback of the sallen-key data filter. 21 rssi buffered received-signal-strength indicator output 22 t/ r transmit/ receive . drive high to put the device in transmit mode. drive low or leave unconnected to put the device in receive mode. it is internally pulled down. this function is also controlled by a configuration register. 23 enable enable. drive high for normal operation. drive low or leave unconnected to put the device into shutdown mode. 24 data receiver data output/transmitter data input 25 clkout divided crystal clock buffered output 26 dv dd digital power-supply voltage. bypass to gnd with 0.01? and 220pf capacitors placed as close to the pin as possible.
detailed description the MAX7032 300mhz to 450mhz cmos transceiver and a few external components provide a complete transmit and receive chain from the antenna to the digi- tal data interface. this device is designed for transmit- ting and receiving ask and fsk data. all transmit frequencies are generated by a fractional-n-based syn- thesizer, allowing for very fine frequency steps in incre- ments of f xtal / 4096. the receive lo is generated by a traditional integer-n-based synthesizer. depending on component selection, data rates as high as 33kbps (manchester encoded) or 66kbps (nrz encoded) can be achieved. receiver low-noise amplifier (lna) the lna is a cascode amplifier with off-chip inductive degeneration that achieves approximately 30db of volt- age gain that is dependent on both the antenna match- ing network at the lna input, and the lc tank network between the lna output and the mixer inputs. the off-chip inductive degeneration is achieved by connecting an inductor from lnasrc to agnd. this inductor sets the real part of the input impedance at lnain, allowing for a more flexible match for low-input impedance such as a pc board trace antenna. a nomi- nal value for this inductor with a 50 ? input impedance is 12nh at 315mhz and 10nh at 434mhz, but the inductance is affected by pc board trace length. lnasrc can be shorted to ground to increase sensitiv- ity by approximately 1db, but the input match must then be reoptimized. the lc tank filter connected to lnaout consists of l5 and c9 (see the typical application circuit ). select l5 and c9 to resonate at the desired rf input frequency. the resonant frequency is given by: where l total = l5 + l parasitics and c total = c9 + c parasitics . l parasitics and c parasitics include inductance and capacitance of the pc board traces, package pins, mixer input impedance, lna output impedance, etc. these parasitics at high frequencies cannot be ignored, and can have a dramatic effect on the tank fil- ter center frequency. lab experimentation must be done to optimize the center frequency of the tank. the total parasitic capacitance is generally between 5pf and 7pf. automatic gain control (agc) when the agc is enabled, it monitors the rssi output. when the rssi output reaches 1.28v, which corre- sponds to an rf input level of approximately -55dbm, the agc switches on the lna gain-reduction attenua- tor. the attenuator reduces the lna gain by 36db, thereby reducing the rssi output by about 540mv to 740mv. the lna resumes high-gain mode when the rssi output level drops back below 680mv (approxi- mately -59dbm at the rf input) for a programmable interval called the agc dwell time. the agc has a hys- teresis of approximately 4db. with the agc function, the rssi dynamic range is increased, allowing the MAX7032 to reliably produce an ask output for rf input levels up to 0dbm with a modulation depth of 18db. agc is not required and can be disabled in either ask or fsk mode. agc is not necessary for fsk mode because large received signal levels do not affect fsk performance. f lc total total = 1 2 MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll ______________________________________________________________________________________ 13 pin description (continued) pin name function 27 hv in high-voltage supply input. for 3v operation, connect hv in to pav dd , av dd , and dv dd . for 5v operation, tie only hv in to 5v. bypass hv in to gnd with 0.01? and 220pf capacitors placed as close to the pin as possible. 28 cs serial interface active-low chip select 29 dio serial interface serial data input/output 30 sclk serial interface clock input 31 xtal1 crystal input 1. bypass to gnd if xtal2 is driven by an ac-coupled external reference. 32 xtal2 crystal input 2. xtal2 can be driven from an ac-coupled external reference. ep gnd exposed paddle. solder evenly to the board? ground plane for proper operation.
mixer a unique feature of the MAX7032 is the integrated image rejection of the mixer. this eliminates the need for a costly front-end saw filter for many applications. the advantage of not using a saw filter is increased sensitivity, simplified antenna matching, less board space, and lower cost. the mixer cell is a pair of double-balanced mixers that perform an iq downconversion of the rf input to the 10.7mhz intermediate frequency (if) with low-side injection (i.e., f lo = f rf - f if ). the image-rejection circuit then combines these signals to achieve a typical 46db of image rejection over the full temperature range. low- side injection is required as high-side injection is not possible due to the on-chip image rejection. the if out- put is driven by a source follower, biased to create a driving impedance of 330 ? to interface with an off-chip 330 ? ceramic if filter. the voltage-conversion gain dri- ving a 330 ? load is approximately 20db. note that the mixin+ and mixin- inputs are functionally identical. integer-n phase-locked loop (pll) the MAX7032 utilizes a fixed integer-n pll to generate the receive lo. all pll components, including the loop fil- ter, vco, charge pump, asynchronous 24x divider, and phase-frequency detector are integrated on-chip. the loop bandwidth is approximately 500khz. the relationship between rf, if, and reference frequencies is given by: f ref = (f rf ?f if ) / 24 intermediate frequency (if) the if section presents a differential 330 ? load to pro- vide matching for the off-chip ceramic filter. the inter- nal six ac-coupled limiting amplifiers produce an overall gain of approximately 65db, with a bandpass fil- ter type response centered near the 10.7mhz if fre- quency with a 3db bandwidth of approximately 10mhz. for ask data, the rssi circuit demodulates the if to baseband by producing a dc output proportional to the log of the if signal level with a slope of approxi- mately 15mv/db. for fsk, the limiter output is fed into a pll to demodulate the if. the fsk demodulation slope is approximately 2.0mv/khz. fsk demodulator the fsk demodulator uses an integrated 10.7mhz pll that tracks the input rf modulation and converts the fre- quency deviation into a voltage difference. the pll is illustrated in figure 1. the input to the pll comes from the output of the if limiting amplifiers. the pll control voltage responds to changes in the frequency of the input signal with a nominal gain of 2.0mv/khz. for exam- ple, an fsk peak-to-peak deviation of 50khz generates a 100mv p-p signal on the control line. this control volt- age is then filtered and sliced by the baseband circuitry. the fsk demodulator pll requires calibration to over- come variations in process, voltage, and temperature. for more information on calibrating the fsk demodula- tor, see the calibration section. the maximum calibra- tion time is 150?. in discontinuous receive (drx) mode, the fsk demodulator calibration occurs auto- matically just after the ic exits sleep mode. data filter the data filter for the demodulated data is implemented as a 2nd-order lowpass sallen-key filter. the pole loca- tions are set by the combination of two on-chip resistors and two external capacitors. adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. the corner frequency in khz should be set to approximately 3 times the fastest expected manchester data rate in kbps from the trans- mitter (1.5 times the fastest expected nrz data rate) for ask. for fsk, the corner frequency should be set to approximately 2 times the fastest expected manchester data rate in kbps from the transmitter (1 times the fastest expected nrz data rate). keeping the corner frequency near the data rate rejects any noise at higher frequen- cies, resulting in an increase in receiver sensitivity. table 1 lists coefficients to calculate cf1 and cf2. filter type a b butterworth (q = 0.707) 1.414 1.000 bessel (q = 0.577) 1.3617 0.618 table 1. coefficients to calculate cf1 and cf2 MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll 14 ______________________________________________________________________________________ loop filter phase detector if limiting amps to fsk baseband filter and data slicer 10.7mhz vco 2.0mv/khz charge pump figure 1. fsk demodulator pll block diagram
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll ______________________________________________________________________________________ 15 the configuration shown in figure 2 can create a butterworth or bessel response. the butterworth filter offers a very flat amplitude response in the passband and a rolloff rate of 40db/decade for the two-pole filter. the bessel filter has a linear phase response, which works well for filtering digital data. to calculate the value of the capacitors, use the following equations, along with the coefficients in table 1: where f c is the desired 3db corner frequency. for example, choose a butterworth filter response with a corner frequency of 5khz: choosing standard capacitor values changes c f1 to 470pf and c f2 to 220pf. in the typical application circuit , c f1 and c f2 are named c16 and c17, respectively. data slicer the data slicer takes the analog output of the data filter and converts it to a digital signal. this is achieved by using a comparator and comparing the analog input to a threshold voltage. the threshold voltage is set by the voltage on the ds- pin, which is connected to the nega- tive input of the data-slicer comparator. numerous configurations can be used to generate the data-slicer threshold. for example, the circuit in figure 3 shows a simple method using only one resistor and one capacitor. this configuration averages the analog output of the filter and sets the threshold to approxi- mately 50% of that amplitude. with this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. the values of r and c affect how fast the thresh- old tracks the analog amplitude. be sure to keep the corner frequency of the rc circuit much lower (about 10 times) than the lowest expected data rate. with this configuration, a long string of nrz zeros or ones can cause the threshold to drift. this configuration works best if a coding scheme, such as manchester coding, which has an equal number of zeros and ones, is used. figure 4 shows a configuration that uses the positive and negative peak detectors to generate the threshold. this configuration sets the threshold to the midpoint between a high output and a low output of the data filter. peak detectors the maximum peak detector (pdmax) and minimum peak detector (pdmin), with resistors and capacitors shown in figure 4, create dc output voltages equal to the high and low peak values of the filtered ask or fsk demodulated signals. the resistors provide a path for the capacitors to discharge, allowing the peak detec- tors to dynamically follow peak changes of the data fil- ter output voltages. c k khz pf c k khz pf f f 1 2 1 000 1 414 100 3 14 5 450 1 414 4 100 3 14 5 225 = = . ( . )( )( . )( ) . ( )( )( . )( ) ? ? c b ak f c a kf f c f c 1 2 100 4 100 = = ()()() ()()() ? ? MAX7032 c ds- ds+ r data slicer data figure 3. generating data slicer threshold using a lowpass filter MAX7032 rssi or fsk demod 100k ? c f2 c f1 100k ? df op+ ds+ figure 2. sallen-key lowpass data filter
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll 16 ______________________________________________________________________________________ the maximum and minimum peak detectors can be used together to form a data slicer threshold voltage at a value midway between the maximum and minimum voltage levels of the data stream (see the data slicer section and figure 4). the rc time constant of the peak-detector combining network should be set to at least 5 times the data period. if there is an event that causes a significant change in the magnitude of the baseband signal, such as an agc gain switch or a power-up transient, the peak detectors may ?atch?a false level. if a false peak is detected, the slicing level is incorrect. the MAX7032 has a fea- ture called peak-detector track enable (trk_en), where the peak-detector outputs can be reset (see figure 5). if trk_en is set (logic 1), both the maximum and minimum peak detectors follow the input signal. when trk_en is cleared (logic 0), the peak detectors revert to their normal operating mode. the trk_en function is automatically enabled for a short time when- ever the ic is first powered up, or transitions from trans- mit to receive mode, or recovers from the sleep portion of drx mode, or when an agc gain switch occurs regardless of the bit setting. since the peak detectors exhibit a fast-attack/slow-decay response, this feature allows for an extremely fast startup or agc recovery. see figure 6 for an illustration of a fast-recovery sequence. in addition to the automatic control of this function, the trk_en bits can be controlled through the serial interface (see the serial control interface section). transmitter power amplifier (pa) the pa of the MAX7032 is a high-efficiency, open- drain, class c amplifier. the pa with proper output- matching network can drive a wide range of antenna impedances, which includes a small-loop pc board trace and a 50 ? antenna. the output-matching network for a 50 ? antenna is shown in the typical application circuit . the output-matching network suppresses the carrier harmonics and transforms the antenna imped- ance to an optimal impedance at paout (pin 5). the optimal impedance at paout is 250 ? . when the output-matching network is properly tuned, the pa transmits power with a high overall efficiency of up to 32%. the efficiency of the pa itself is more than 46%. the output power is set by an external resistor at paout, and is also dependent on the external antenna and antenna-matching network at the pa output. MAX7032 pdmin to slicer input baseband filter minimum peak detector maximum peak detector pdmax trk_en = 1 trk_en = 1 figure 5. peak-detector track enable figure 6. fast receiver recovery in fsk mode utilizing peak detectors 200mv/div data output 2v/div min peak detector max peak detector receiver enabled, trk_en set trk_en cleared filter output data output 100 s/div MAX7032 c pdmax pdmin r c r data slicer data peak det peak det figure 4. generating data slicer threshold using the peak detectors
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll ______________________________________________________________________________________ 17 envelope shaping the MAX7032 features an internal envelope-shaping resistor, which connects between the open-drain output of the pa and the power supply (see typical application circuit ). the envelope-shaping resistor slows the turn-on/turn-off of the pa in ask mode, and results in a smaller spectral width of the modulated pa output signal. fractional-n pll the MAX7032 utilizes a fully integrated fractional-n pll for its transmit frequency synthesizer. all pll compo- nents, including the loop filter, are included on chip. the loop bandwidth is approximately 200khz. the 16- bit fractional-n topology allows the transmit frequency to be adjusted in increments of f xtal / 4096. the fine- frequency-adjustment capability enables the use of a single crystal, as the transmit frequency can be set within 2khz of the receive frequency. the fractional-n topology also allows exact fsk fre- quency deviations to be programmed, completely elim- inating the problems associated with generating frequency deviations by crystal oscillator pulling. the integer and fractional portions of the pll divider ratio set the transmit frequency. the example below shows how to calculate f xtal and how to determine the correct values to be loaded to register txlow (register 0x0d and 0x0e) and txhigh (registers 0x0f and 0x10): assume the receiver/ask transmit frequency = 315mhz, and if = 10.7mhz: and due to the nature of the transmit pll frequency divider, a fixed offset of 16 must be subtracted from the trans- mit pll divider ratio for programming the MAX7032? transmit frequency registers. to determine the value to program the MAX7032? transmit frequency registers, convert the decimal value of the following equation to the nearest hexadecimal value: in this example, the rounded decimal value is 36,225, or 8d81 hexadecimal. the upper byte (8d) is loaded into register 0x0d, and the low byte (81) is loaded into register 0x0e. in fsk mode, the transmit frequencies equal the upper and lower frequencies that are programmed into the MAX7032? transmit frequency registers. calculate the upper frequency in the same way as shown above. in ask mode, the transmit frequency equals the lower fre- quency that is programmed into the MAX7032? trans- mit frequency registers. power-supply connections the MAX7032 can be powered from a 2.1v to 3.6v supply or a 4.5v to 5.5v supply. if a 4.5v to 5.5v supply is used, then the on-chip linear regulator reduces the 5v supply to the 3v needed to operate the chip. to operate the MAX7032 from a 3v supply, connect pav dd , av dd , dv dd , and hv in to the 3v supply. when using a 5v supply, connect the supply to hv in only and connect av dd , pav dd , and dv dd together. in both cases, bypass dv dd , pav dd and hv in to gnd with a 0.01? and 220pf capacitor and bypass av dd to gnd with a 0.1? and 220pf capacitor. bypass t/ r , enable, data, cs , dio, and sclk with 10pf capaci- tors to gnd. place all bypass capacitors as close to the respective pins as possible. transmit/receive antenna switch the MAX7032 features an internal spst rf switch, which, when combined with a few external compo- nents, allows the transmit and receive pins to share a common antenna (see the typical application circuit) . in receive mode, the switch is open and the power amplifier is shut down, presenting a high impedance to minimize the loading of the lna. in transmit mode, the switch closes to complete a resonant tank circuit at the pa output and forms an rf short at the input to the lna. in this mode, the external passive components couple the output of the pa to the antenna to protect the lna input from strong transmitted signals. the switch state is controlled either by an external digi- tal input or by the t/ r bit, which is bit 6 in the configura- tion 0 register, t/ r . drive the t/ r pin high to put the device in transmit mode; drive the t/ r pin low to put the device in receive mode. f f decimal value to program transmit frequency registers rf xtal ? ? ? ? ? ? ? = 16 4096 f f transmit pll divider ratio rf xtal == 24 8439 . f f mhz xtal rf = ? = (.) . 10 7 24 12 67917
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll 18 ______________________________________________________________________________________ crystal oscillator (xtal) the xtal oscillator in the MAX7032 is designed to pre- sent a capacitance of approximately 3pf between the xtal1 and xtal2 pins. in most cases, this corre- sponds to a 4.5pf load capacitance applied to the external crystal when typical pc board parasitics are added. it is very important to use a crystal with a load capacitance that is equal to the capacitance of the MAX7032 crystal oscillator plus pc board para- sitics. if a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing an error in the reference frequency. crystals designed to operate with higher differential load capacitance always pull the reference frequency higher. in actuality, the oscillator pulls every crystal. the crys- tal? natural frequency is really below its specified fre- quency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. this pulling is already accounted for in the specification of the load capacitance. additional pulling can be calculated if the electrical parameters of the crystal are known. the frequency pulling is given by: where: f p is the amount the crystal frequency is pulled in ppm. c m is the motional capacitance of the crystal. c case is the case capacitance. c spec is the specified load capacitance. c load is the actual load capacitance. when the crystal is loaded as specified, i.e., c load = c spec , the frequency pulling equals zero. serial control interface communication protocol the MAX7032 programs through a 3-wire interface. the data input must follow the timing diagrams shown in figures 7, 8, and 9. note that the dio line must be held low while cs is high. this is to prevent the MAX7032 from entering dis- continuous receive mode if the drx bit is high. the data is latched on the rising edge of sclk, and there- fore must be stable before that edge. the data sequencing is msb first, the command (c[1:0] see table 2), the register address (a[5:0] see table 3), and the data (d[7:0] see table 4). f c cc cc p m case load case spec = + ? + ? ? ? ? ? ? 2 11 10 6 c[1:0] description 0x0 no operation 0x1 write data 0x2 read data 0x3 master reset table 2. command bits hi-z data out cs t css t ds t dh t ch t cl t th data in t dv hi-z t do t csh t tr hi-z sclk dio t cs t sc d7 d0 figure 7. serial interface timing diagram
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll ______________________________________________________________________________________ 19 register a[5:0] register name description 0x00 power configuration enables/disables the lna, agc, mixer, baseband, peak detectors, pa, and rssi output (see table 5). 0x01 control controls agc lock, gain state, peak-detector tracking, polling timer and fsk calibration, clock signal output, and sleep mode (see table 6). 0x02 configuration0 sets options for modulation, tx/rx mode, manual-gain mode, discontinuous receive mode, off-timer and on-timer prescalers (see table 7). 0x03 configuration1 sets options for automatic fsk calibration, clock output, output clock divider ratio, agc dwell timer (see tables 8, 10, 11, and 12). 0x05 oscillator frequency sets the internal clock frequency divisor. this register must be set to the integer result of f xtal / 100khz (see the oscillator frequency register section). 0x06 off timer? off (upper byte) 0x07 off timer? off (lower byte) sets the duration that the MAX7032 remains in low-power mode when drx is active (see table 12). 0x08 cpu recovery timer? cpu increases maximum time the MAX7032 stays in lower power mode while cpu wakes up when drx is active (see table 13). 0x09 rf settling timer? rf (upper byte) 0x0a rf settling timer? rf (lower byte) during the time set by the rf settling timer, the MAX7032 is powered on with the peak detectors and the data outputs disabled to allow time for the rf section to settle. dio must be driven low at any time during t low = t cpu + t rf + t on or the timer sequence restarts (see table 14). 0x0b on timer? on (upper byte) 0x0c on timer? on (lower byte) sets the duration that the MAX7032 remains in active mode when drx is active (see table 15). 0x0d transmitter low-frequency setting?xlow (upper byte) 0x0e transmitter low-frequency setting?xlow (lower byte) sets the low frequency (fsk) of the transmitter or the carrier frequency of ask for the fractional-n synthesizer. 0x0f transmitter high-frequency setting?xhigh (upper byte) 0x10 transmitter high-frequency setting?xhigh (lower byte) sets the high frequency (fsk) of the transmitter for the fractional-n synthesizer. 0x1a status register (read only) provides status for pll lock, agc state, crystal operation, polling timer, and fsk calibration (see table 9). table 3. register summary
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll 20 ______________________________________________________________________________________ cs dio sclk cs dio sclk 0 0 0 0 0 0 0 0 a3 a2 a1 a0 read command read command address data r7 r6 r5 r4 r3 r2 r1 r0 r0 r7 register data register data 0 0 0 0 0 0 0 0 a3 a2 a1 a0 address data r7 r6 r5 r4 r3 r2 r1 register data a3 16 bits of data 8 bits of data 1 0 a5 a4 1 0 a5 a4 figure 9. read command on a 3-wire serial interface c1 c0 a5 a4 a3 a2 a1 a0 d3 d2 d1 d0 d7 d6 d5 d4 command address data cs dio sclk figure 8. data input diagram dio is selected as an output of the MAX7032 for the fol- lowing cs cycle whenever a read command is received. the cpu must tri-state the dio line on the cycle of cs that follows a read command, so the MAX7032 can drive the data output line. figure 9 shows the diagram of the 3-wire interface. note that the user can choose to send either 16 cycles of slck or just eight cycles as all the registers are 8-bits wide. the user must drive dio low at the end of the read sequence. the master reset command (0x3) (see table 2) sends a reset signal to all the internal registers of the MAX7032 just like a power-off and power-on sequence would do. the reset signal remains active for as long as cs is high after the command is sent.
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll ______________________________________________________________________________________ 21 continuous receive mode (drx = 0) in continuous receive mode, individual analog modules can be powered on directly through the power configu- ration register (register 0x00). the sleep bit (bit 0 in register 0x01) overrides the power configuration regis- ters and puts the device into deep-sleep mode when set. it is also necessary to write the frequency divisor of the external crystal in the oscillator frequency register (register 0x05) to optimize image rejection and to enable accurate calibration sequences for the polling timer and the fsk demodulator. this number is the integer result of f xtal / 100khz. if the fsk receive function is selected, it is necessary to perform an fsk calibration to allow operation; other- wise, the demodulator is saturated. polling timer cali- bration is not necessary. see the calibration section for more information. discontinuous receive mode (drx = 1) in the discontinuous receive mode (drx = 1), the receiver modules set to logic 1 by the power register (0x00) of the MAX7032 toggle between off and on, according to internal timers t off , t cpu , t rf , and t on . it is also necessary to write the frequency divisor of the external crystal in the oscillator frequency register (reg- ister 0x05). this number is the integer result of f xtal / 100khz. before entering the discontinuous receive mode for the first time, it is also necessary to calibrate the timers (see the calibration section ). the MAX7032 uses a series of internal timers (t off , t cpu , t rf , and t on ) to control its power-up sequence. the timer sequence begins when both cs and dio are one. the MAX7032 has an internal pullup on the dio pin, so the user must tri-state the dio line when cs goes high. the external cpu can then go to a sleep mode during t off . a high-to-low transition on dio, or a low level on dio serves as the wake-up signal for the cpu, which must then start its wake-up procedure, and drive dio low before t low expires (t cpu + t rf + t on ). once t rf expires and t on is active, the MAX7032 enables the data output. the cpu must then keep dio low for as long as it may need to analyze any received data. releasing dio after t on expires causes the MAX7032 to pull up dio, reinitiating the t off timer. data name (address) d7 d6 d5 d4 d3 d2 d1 d0 power[7:0] (0x00) lna agc mixer baseb pkdet pa rssio x contrl[7:0] (0x01) agclk gain trk_en pcal fcal ckout sleep conf0[7:0] (0x02) mode t/ r mgain drx ofps1 ofps0 onps1 onps0 conf1[7:0] (0x03) acal clkof cdiv1 cdiv0 dt2 dt1 dt0 osc[7:0] (0x05) osc7 osc6 osc5 osc4 osc3 osc2 osc1 osc0 t off [15:8] (0x06) t off 15 t off 14 t off 13 t off 12 t off 11 t off 10 t off 9t off 8 t off [7:0] (0x07) t off 7t off 6t off 5t off 4t off 3t off 2t off 1t off 0 t cpu [7:0] (0x08) t cpu 7t cpu 6t cpu 5t cpu 4t cpu 3t cpu 2t cpu 1t cpu 0 t rf [15:8] (0x09) t rf 15 t rf 14 t rf 13 t rf 12 t rf 11 t rf 10 t rf 9t rf 8 t rf [7:0] (0x0a) t rf 7t rf 6t rf 5t rf 4t rf 3t rf 2t rf 1t rf 0 t on [15:8] (0x0b) t on 15 t on 14 t on 13 t on 12 t on 11 t on 10 t on 9t on 8 t on [7:0] (0x0c) t on 7t on 6t on 5t on 4t on 3t on 2t on 1t on 0 txlow[15:8] (0x0d) txl15 txl14 txl13 txl12 txl11 txl10 txl9 txl8 txlow[7:0] (0x0e) txl7 txl6 txl5 txl4 txl3 txl2 txl1 txl0 txhigh[15:8] (0x0f) txh15 txh14 txh13 txh12 txh11 txh10 txh9 txh8 txhigh[7:0] (0x10) txh7 txh6 txh5 txh4 txh3 txh2 txh1 txh0 status[7:0] (0x1a) lckd gains clkon 0 0 0 pcald fcald table 4. register configuration
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll 22 ______________________________________________________________________________________ bit id bit name bit location (0 = lsb) function agclk agc locking feature 7 1 = enable agc lock 0 = disable agc lock gain gain state 6 1 = force manual high-gain state if mgain = 1 0 = force manual low-gain state if mgain = 1 trk_en manual peak-detector tracking 5 1 = force manual peak-detector tracking 0 = release peak-detector tracking x none 4 not used pcal polling timer calibration 3 1 = perform polling timer calibration automatically reset to zero once calibration is completed fcal fsk calibration 2 1 = perform fsk calibration automatically reset to zero once calibration is completed ckout crystal clock output enable 1 1 = enable crystal clock output 0 = disable crystal clock output sleep sleep mode 0 1 = deep-sleep mode, regardless the state of enable pin 0 = normal operation table 6. control register (address: 0x01) bit id bit name bit location (0 = lsb) function lna lna enable 7 1 = enable lna 0 = disable lna agc agc enable 6 1 = enable agc 0 = disable agc mixer mixer enable 5 1 = enable mixer 0 = disable mixer baseb baseband enable 4 1 = enable baseband 0 = disable baseband pkdet peak-detector enable 3 1 = enable peak detector 0 = disable peak detector pa transmitter pa enable 2 1 = enable pa 0 = disable pa rssio rssi amplifier enable 1 1 = enable buffer 0 = disable buffer x none 0 not used table 5. power-configuration register (address: 0x00)
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll ______________________________________________________________________________________ 23 bit id bit name bit location (0 = lsb) function mode fsk or ask modulation 7 1 = enable fsk for both receive and transmit 0 = enable ask for both receive and transmit t/ r transmit or receive 6 1 = enable transmit mode of the transceiver, regardless the state of pin t/ r 0 = enable receive mode of the transceiver when pin t/ r = 0 mgain manual gain mode 5 1 = enable manual-gain mode 0 = disable manual-gain mode drx discontinuous receive mode 4 1 = enable drx 0 = disable drx ofps1 off-timer prescaler 3 ofps0 off-timer prescaler 2 sets the time base for the off timer (see the off timer section) onps1 on-timer prescaler 1 onps0 on-timer prescaler 0 sets the time base for the on timer (see the on timer section) table 7. configuration 0 register (address: 0x02) bit id bit name bit location (0 = lsb) function x none 7 not used acal automatic fsk calibration 6 1 = enable automatic fsk calibration approximately once every 60s 0 = disable automatic fsk calibration clkof continuous clock output (even during t off or when en pin is low) 5 1 = enable continuous clock output when ckout = 1 0 = continuous clock output; if ckout = 1, clock output is active during t on (drx mode) or when en pin is high (continuous receive mode) cdiv1 crystal divider 4 clkout crystal-divider msb cdiv0 crystal divider 3 clkout crystal-divider lsb dt2 agc dwell timer 2 agc dwell timer msb dt1 agc dwell timer 1 agc dwell timer dt0 agc dwell timer 0 agc dwell timer lsb table 8. configuration 1 register (address: 0x03)
oscillator frequency register (address 0x05) the MAX7032 has an internal frequency divider that divides down the crystal frequency to 100khz. the MAX7032 uses the 100khz clock signal when calibrat- ing itself and also to set image-rejection frequency. the hexadecimal value written to the oscillator frequency register is the nearest integer result of f xtal / 100khz. for example, if data is being received at 315mhz, the crystal frequency is 12.67917mhz. dividing the crystal frequency by 100khz and rounding to the nearest inte- ger gives 127, or 0x7f hex. so for 315mhz, 0x7f would be written to the oscillator frequency register. agc dwell timer (address 0x03) the agc dwell timer holds the agc in low-gain state for a set amount of time after the power level drops below the agc switching threshold. after that set amount of time, if the power level is still below the agc threshold, the lna goes into high-gain state. this is important for ask since the modulated data may have a high level above the threshold and a low level below the threshold, which without the dwell timer would cause the agc to switch on every bit. MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll 24 ______________________________________________________________________________________ ckout cdiv1 cdiv0 clockout frequency 0 x x disabled at logic 0 10 0f xtal 10 1f xtal / 2 11 0f xtal / 4 11 1f xtal / 8 table 10. clock output divider ratio configuration bit id bit name bit location (0 = lsb) function lckd lock detect 7 1 = internal pll is locked 0 = internal pll is not locked so the MAX7032 does not receive or transmit data gains agc gain state 6 1 = lna in high-gain state 0 = lna in low-gain state clkon clock/crystal alive 5 1 = valid clock at crystal inputs 0 = no valid clock signal seen at the crystal inputs x none 4 zero x none 3 zero x none 2 zero pcald polling timer calibration done 1 1 = polling timer calibration is completed 0 = polling timer calibration is in progress or not completed fcald fsk calibration done 0 1 = fsk calibration is completed 0 = fsk calibration is in progress or not completed table 9. status register (read only) (address: 0x1a)
the agc dwell time is dependent on the crystal fre- quency and the bit settings of the agc dwell timer. to calculate the dwell time, use the following equation: where k is an odd integer in decimal from 9 to 23; see table 11. to calculate the value of k, use the following equation and use the next odd integer higher than the calculated result: k 3.3 x log 10 (dwell time x f xtal ) for manchester code (50% duty cycle), set the dwell time to at least twice the bit period. for nrz data, set the dwell to greater than the period of the longest string of zeros or ones. for example, using manchester code at 315mhz (f xtal = 12.679mhz) with a data rate of 4kbps (bit period = 125?), the dwell time needs to be greater than 250?: k 3.3 x log 10 (250? x 12.679mhz) 11.553 choose the register value to be the next odd integer value higher than 11.553, which is k = 13. the default value of the agc dwell timer on power-up or rest is zero (k = 9). calibration the MAX7032 must be calibrated to ensure accurate timing of the off timer in discontinuous receive mode or when receiving fsk signals. the first step in calibration is ensuring that the oscillator frequency register (regis- ter: 0x05) has been programmed with the correct divi- sor value (see the oscillator frequency register section). next, enable the mixer to turn the crystal dri- ver on. calibrate the polling timer by setting pcal = 1 in the control register (register 0x01, bit 3). upon completion, the pcald bit in the status register (register 0x1a, bit 1) is 1, and the pcal bit is reset to zero. if using the MAX7032 in continuous receive mode, polling timer calibration is not needed. to calibrate the fsk receiver, set fcal = 1. upon completion, the fcald bit in the status register (regis- ter 0x08) is one, and the fcal bit is reset to zero. when in continuous receive mode and receiving fsk data, recalibrate the fsk receiver after a significant change in temperature or supply voltage. an autocal fea- ture is provided that performs a calibration every minute (acal bit, table 8). when in discontinuous receive mode, the polling timer and fsk receiver (if enabled) are automatically calibrated every wake-up cycle. off timer (t off ) the off timer, t off (see figure 10), is a 16-bit timer that is configured using register 0x06 for the upper byte, register 0x07 for the lower byte, and bits ofps1 and ofps0 in the configuration 0 register (register 0x02, bit 3 and bit 2, respectively). table 12 summarizes the configuration of the t off timer. the ofps1 and ofps0 bits set the size of the shortest time possible (t off time base). the data written to the t off registers (register 0x06 and register 0x07) are multiplied by the time base to give the total t off time. see the example below. on power-up, the off-timer registers are reset to zero and must be written before using drx mode. dwell time f k xtal = 2 MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll ______________________________________________________________________________________ 25 dt2 dt1 dt0 description 0 0 0 k = 9 001 k = 11 010 k = 13 011 k = 15 100 k = 17 101 k = 19 110 k = 21 111 k = 23 table 11. agc dwell timer configuration (address 0x03) ofps1 ofps0 t off time base min t off reg 0x06 = 0x00; reg 0x07 = 0x01 max t off reg 0x06 = 0xff; reg 0x07 = 0xff 0 0 120? 120? 7.86s 0 1 480? 480? 31.46s 1 0 1920? 1.92ms 2 min 6s 1 1 7680? 7.68ms 8 min 23s table 12. off-timer (t off ) configuration
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll 26 ______________________________________________________________________________________ cs dio t off ask_data or fsk_data t cpu t rf t on t off t cpu t rf t on t low figure 10. drx mode sequence of the MAX7032 set ofps1 to be 1 and ofps0 to be 1. that sets the t off time base (1 lsb) to be 7680?. set reg 0x06 and reg 0x07 to be ffff, which is 65535 in decimal. therefore, the total t off is: t off = 7680? x 65535 = 8min 23s during t off , the MAX7032 is operating with very low supply current (23.4? typ), where all its modules are turned off, except for the t off timer itself. upon com- pletion of the t off time, the MAX7032 signals the user by asserting dio low. cpu recovery timer (t cpu ) the cpu recovery timer, t cpu (see figure 10) is used to delay power up of the MAX7032, thereby providing extra power savings and giving the cpu time to com- plete its own power-on sequence. the cpu is signaled to begin powering up when the dio line is pulled low by the MAX7032 at the end of t off . then, t cpu begins counting, while dio is held low by the MAX7032. at the end of t cpu , the t rf counter begins. t cpu is an 8-bit timer, configured through register 0x08. the possible t cpu settings are summarized in table 13. the data written to the t cpu register (register 0x08) is multiplied by 120? to give the total t cpu time. see the example below. on power-up, the cpu timer register is reset to zero and must be written before using drx mode. set reg 0x08 to be ff in hex, which is 255 in decimal. therefore, the total t cpu is: t cpu = 120? x 255 = 30.6ms rf settling timer (t rf ) the rf settling timer, t rf (see figure 10), allows the rf sections of the MAX7032 to power up and stabilize before ask or fsk data is received. t rf begins count- ing once t cpu has expired. at the beginning of t rf , the modules selected in the power control register (register 0x00) are all powered up and the peak detectors are in the track mode and have the t rf period to settle. t rf is a 16-bit timer, configured through register 0x09 (upper byte) and register 0x0a (lower byte). the possi- ble t rf settings are listed in table 14. the data written to the t rf register (register 0x09 and register 0x0a) are multiplied by 120? to give the total t rf time. see the example in the cpu recovery time ( t cpu ) section. on power-up, the rf timer registers are reset to zero and must be written before using drx mode. time base (s) min t cpu reg 0x08 = 0x01 (s) max t cpu reg 0x08 = 0xff (ms) 120 120 30.6 table 13. cpu recovery timer (t cpu ) configuration t rf time base (s) min t rf reg 0x09 = 0x00 reg 0x0a = 0x01 (s) max t rf reg 0x09 = 0xff reg 0x0a = 0xff (s) 120 120 7.86 table 14. rf settling timer (t rf ) configuration
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll ______________________________________________________________________________________ 27 on timer (t on ) the on timer, t on (see figure 10), is a 16-bit timer that is configured through register 0x0b for the upper byte, register 0x0c for the lower byte (table 15). the infor- mation stored in this timer provides an additional way to control the duration of the on time of the receiver. the cpu must begin driving dio low any time during t low = t cpu + t rf + t on . if the cpu fails to drive dio low at the end of t on , dio is pulled high through the internal pullup resistor, and the time sequence is restarted, leaving the MAX7032 powered down. any time the dio line is driven high while the drx = 1, the drx sequence is initiated, as defined in figure 10. in the event that the cpu is processing data, after t on expires, the cpu should keep the MAX7032 awake by holding the dio line low. the data written to the t on register (register 0x0b and register 0x0c) are multiplied by the t on time base (table 15) to give the total t on time. see the example in the off timer ( t off ) section. on power-up, the on-timer register is reset to zero and must be written before using drx mode. transmitter low-frequency register (txlow) the txlow register sets the divider information of the fractional-n synthesizer for the lower transmit frequency in fsk mode. see the example given in the fractional-n pll section. in ask mode, txlow determines the carri- er frequency. transmitter high-frequency register (txhigh) the txhigh register sets the divider information of the fractional-n synthesizer for the upper transmit frequency in the fsk mode. in ask mode, the content of txhigh is not used. the 16-bit register contains the binary rep- resentation of the tx pll divider ratio, which is shown in the example in the fractional-n pll section. applications information output matching to 50 ? ? when matched to a 50 ? system, the MAX7032? pa is capable of delivering +10dbm of output power at v dd = +2.7v. the output of the pa is an open-drain transis- tor that requires external impedance matching and pullup inductance for proper biasing. the pullup induc- tance from the pa to pav dd serves three main purpos- es: it resonates the capacitive pa output, provides biasing for the pa, and becomes a high-frequency choke to prevent rf energy from coupling into v dd . the network also forms a bandpass filter that provides attention for the higher order harmonics. output matching to pc board loop antenna in most applications, the MAX7032 must be impedance matched to a small-loop antenna. the antenna is usual- ly fabricated out of a copper trace on a pc board in a rectangular, circular, or square pattern. the antenna has an impedance that consists of a lossy component and a radiative component. to achieve high radiating efficiency, the radiative component should be as high as possible, while minimizing the lossy component. in addition, the loop antenna has an inherent loop induc- tance associated with it (assuming the antenna is termi- nated to ground). for example, in a typical application, the radiative impedance is less than 0.5 ? , the lossy impedance is less than 0.7 ? , and the inductance is approximately 50nh to 100nh. layout considerations a properly designed pc board is an essential part of any rf/microwave circuit. on high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radia- tion. at high frequencies, trace lengths that are on the order of / 10 or longer act as antennas, where is the wavelength. onps1 onps0 t on time base min t on reg 0x0b = 0x00 reg 0x0c = 0x01 max t on reg 0x0b = 0xff reg 0x0c = 0xff 0 0 120? 120? 7.86s 0 1 480? 480? 31.46s 1 0 1920? 1.92? 2 min 6s 1 1 7680? 7.68? 8 min 23s table 15. on-timer (t on ) configuration
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll 28 ______________________________________________________________________________________ keeping the traces short also reduces parasitic induc- tance. generally, 1in of pc board trace adds about 20nh of parasitic inductance. the parasitic inductance can have a dramatic effect on the effective inductance of a passive component. for example, a 0.5in trace connecting to a 100nh inductor adds an extra 10nh of inductance, or 10%. to reduce parasitic inductance, use wider traces and a solid ground or power plane below the signal traces. also, use low-inductance connections to the ground plane, and place decoupling capacitors as close to all v dd pins and hv in as possible. 1 2 3 4 5 6 7 8 c8 l3 c6 910 11 c10 c12 c9 12 l5 c11 13 in out gnd 14 15 16 y2 c13 17 18 19 20 21 22 23 24 c17 r1 25 26 27 28 29 30 32 31 clock output dio sclk MAX7032 3.0v c23 v dd v dd pav dd rout tx/rx1 tx/rx2 paout av dd lnain lnasrc lnaout mixin+ mixin- ifin+ ifin- pdmin pdmax mixout ds- ds+ op+ df rssi t/r enable data clkout dv dd hvin cs dio sclk xtal1 xtal2 cs c20 c21 y1 l4 c14 c15 data enable c16 transmit/ receive c22 c5 c4 c18 c19 c7 l1 l2 c1 c2 r2 r3* *optional power-adjust resistor c24 exposed paddle c3 l6 v dd v dd v dd typical application circuit
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll ______________________________________________________________________________________ 29 component value for 433.92mhz rf value for 315mhz rf description c1 220pf 220pf 10% c2 680pf 680pf 10% c3 6.8pf 12pf 5% c4 6.8pf 10pf 5% c5 10pf 22pf 5% c6 220pf 220pf 10% c7 0.1? 0.1? 10% c8 100pf 100pf 5% c9 1.8pf 2.7pf ?.1pf c10 100pf 100pf 5% c11 220pf 220pf 10% c12 100pf 100pf 5% c13 1500pf 1500pf 10% c14 0.047? 0.047? 10% c15 0.047? 0.047? 10% c16 470pf 470pf 10% c17 220pf 220pf 10% c18 220pf 220pf 10% c19 0.01? 0.01? 10% c20 100pf 100pf 5% c21 100pf 100pf 5% c22 220pf 220pf 10% c23 0.01? 0.01? 10% c24 0.01? 0.01? 10% l1 22nh 27nh coilcraft 0603cs l2 22nh 30nh coilcraft 0603cs l3 22nh 30nh coilcraft 0603cs l4 10nh 12nh coilcraft 0603cs l5 16nh 30nh murata lqw18a l6 68nh 100nh coilcraft 0603cs r1 100k ? 100k ? 5% r2 100k ? 100k ? 5% r3 0 ? 0 ? y1 17.63416mhz 12.67917mhz crystal, 4.5pf load capacitance y2 10.7mhz ceramic filter 10.7mhz ceramic filter murata sfecv10.7 series table 16. component values for typical application circuit note: component values vary depending on pc board layout.
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll 30 ______________________________________________________________________________________ lna 90 0 rssi if limiting amps ask 100k ? 100k ? data filter 7 8 9 10 11 12 14 13 fsk demodulator fsk 20 19 rx data 18 15 16 17 30 28 29 24 21 23 22 serial interface and digital logic 31 32 crystal oscillator 1/k 25 27 3.0v regulator 6 26 pa MAX7032 5 1 2 rx vco rx frequency divider phase detector charge pump loop filter tx frequency divider ? modulator i q tx vco exposed paddle lnain lnasrc tx/rx1 tx/rx2 xtal1 xtal2 clkout hv in av dd rout pav dd paout t/r dv dd enable data dio cs sclk ds- pdmax pdmin ds+ rssi op+ df ifin+ ifin- mixout mixin- mixin+ lnaout 3 4 functional diagram
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll ______________________________________________________________________________________ 31 chip information process: cmos top view 24 23 22 21 20 19 18 1234567 10 11 12 13 14 15 16 31 30 29 28 27 26 25 MAX7032 thin qfn dv dd clkout hv in cs dio sclk xtal1 32 xtal2 data enable t/r rssi df op+ ds+ 17 ds- pdmax pdmin ifin+ ifin- mixout mixin- mixin+ 9 lnaout lnain av dd 8 lnasrc paout tx/rx2 tx/rx1 rout pav dd pin configuration
MAX7032 low-cost, crystal-based, programmable, ask/fsk transceiver with fractional-n pll maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 32 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. MAX7032 MAX7032 MAX7032 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qfn thin.eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 d/2 d2/2 l c l c e e l c c l k l l detail b l l1 e xxxxx marking h 1 2 21-0140 package outline, 16, 20, 28, 32, 40l thin qfn, 5x5x0.8mm -drawing not to scale- l e/2 common dimensions 3.35 3.15 t2855-1 3.25 3.35 3.15 3.25 max. 3.20 exposed pad variations 3.00 t2055-2 3.10 d2 nom. min. 3.20 3.00 3.10 min. e2 nom. max. ne nd pkg. codes 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220, except exposed pad dimension for t2855-1, t2855-3, and t2855-6. notes: symbol pkg. n l1 e e d b a3 a a1 k 10. warpage shall not exceed 0.10 mm. jedec t1655-1 3.20 3.00 3.10 3.00 3.10 3.20 0.70 0.80 0.75 4.90 4.90 0.25 0.25 0 -- 4 whhb 4 16 0.35 0.30 5.10 5.10 5.00 0.80 bsc. 5.00 0.05 0.20 ref. 0.02 min. max. nom. 16l 5x5 3.10 t3255-2 3.00 3.20 3.00 3.10 3.20 2.70 t2855-2 2.60 2.60 2.80 2.70 2.80 l 0.30 0.50 0.40 -- - -- - whhc 20 5 5 5.00 5.00 0.30 0.55 0.65 bsc. 0.45 0.25 4.90 4.90 0.25 0.65 - - 5.10 5.10 0.35 20l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-1 28 7 7 5.00 5.00 0.25 0.55 0.50 bsc. 0.45 0.25 4.90 4.90 0.20 0.65 - - 5.10 5.10 0.30 28l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-2 32 8 8 5.00 5.00 0.40 0.50 bsc. 0.30 0.25 4.90 4.90 0.50 - - 5.10 5.10 32l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. 0.20 0.25 0.30 down bonds allowed no yes 3.10 3.00 3.20 3.10 3.00 3.20 t2055-3 3.10 3.00 3.20 3.10 3.00 3.20 t2055-4 t2855-3 3.15 3.25 3.35 3.15 3.25 3.35 t2855-6 3.15 3.25 3.35 3.15 3.25 3.35 t2855-4 2.60 2.70 2.80 2.60 2.70 2.80 t2855-5 2.60 2.70 2.80 2.60 2.70 2.80 t2855-7 2.60 2.70 2.80 2.60 2.70 2.80 3.20 3.00 3.10 t3255-3 3.20 3.00 3.10 3.20 3.00 3.10 t3255-4 3.20 3.00 3.10 no no no no no no no no yes yes yes yes 3.20 3.00 t1655-2 3.10 3.00 3.10 3.20 yes no 3.20 3.10 3.00 3.10 t1655n-1 3.00 3.20 3.35 3.15 t2055-5 3.25 3.15 3.25 3.35 yes 3.35 3.15 t2855n-1 3.25 3.15 3.25 3.35 no 3.35 3.15 t2855-8 3.25 3.15 3.25 3.35 yes 3.20 3.10 t3255n-1 3.00 no 3.20 3.10 3.00 l 0.40 0.40 ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** see common dimensions table 0.15 11. marking is for package orientation reference only. h 2 2 21-0140 package outline, 16, 20, 28, 32, 40l thin qfn, 5x5x0.8mm -drawing not to scale- 12. number of leads shown are for reference only. 3.30 t4055-1 3.20 3.40 3.20 3.30 3.40 ** yes 0.05 00.02 0.60 0.40 0.50 10 ----- 0.30 40 10 0.40 0.50 5.10 4.90 5.00 0.25 0.35 0.45 0.40 bsc. 0.15 4.90 0.25 0.20 5.00 5.10 0.20 ref. 0.70 min. 0.75 0.80 nom. 40l 5x5 max. 13. lead centerlines to be at true position as defined by basic dimension "e", 0.05.


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